Stephen S. Pawlowski

Stephen S. Pawlowski

Intel Senior Fellow
GM, IAG & DCSG Pathfinding
CTO, Datacenter & Connected Systems Group
Stephen S. Pawlowski

Presenter at the Computing @ Exascale symposium

Stephen S. Pawlowski is responsible for ensuring architectural consistency across all Intel® Architecture and implementation of initiatives such as security and manageability across Intel® Core™ and Intel® Atom™ product lines. Pawlowski joined Intel in 1982. He led the design of the first Multibus I Single Board Computer based on the 386 processor. He was a lead architect and designer for Intel's early desktop PC and high performance server products and was the co-architect for Intel's first P6 based server chipsets. He helped define the system bus interfaces for Intel's P6 family processors, the Pentium® 4 processor and Itanium™ processor. He also created and led the research for Intel's agile radio architecture for a future generation of wireless products, he was the director of Corporate Technology Group's Microprocessor Technology Lab and prior to his current assignment, he was the CTO of the Digital Enterprise Group (DEG) and General Manager of the DEG Architecture and Planning. Pawlowski graduated from the Oregon Institute of Technology in 1982 with bachelor's degrees in electrical engineering technology and computer systems engineering technology, and received a master's degree in computer science and engineering from the Oregon Graduate Institute in 1993. Pawlowski holds 56 patents in the area of system, and microprocessor technologies. He has received three Intel Achievement Awards.